Configurable capacitor

ABSTRACT

A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/085,514, filed Oct. 30, 2020, for “CONFIGURABLE CAPACITOR,” whichclaims the benefit of U.S. Provisional Application No. 62/929,614, filedNov. 1, 2019; for “CONFIGURABLE CAPACITOR,” the contents of which arehereby incorporated herein by reference in their entirety.

BACKGROUND

Unless otherwise indicated herein, the materials described in thissection are not prior art to the claims in this application and are notadmitted to be prior art by inclusion in this section.

Switching DC/DC voltage regulators, as well as other electroniccircuits, use decoupling capacitors to reduce voltage ripple and noiseon input and output voltage lines. Miniaturization and integration ofelectronic circuit components leads to need for multiple high density,small footprint capacitors. One approach has been to stack multiplediscrete capacitors on a printed circuit board or integrated circuitpackage. This approach can result in poor overall capacitorcharacteristics, a larger circuit footprint, and wasted board spacebetween the capacitors due to finite spacing rules for discretecapacitors.

SUMMARY

Aspects of the present disclosure relate to capacitors, and moreparticularly, though not necessarily exclusively, configurablecapacitors in an integrated package.

According to various aspects there is provided a configurablecapacitance device. In some aspects, the configurable capacitance devicemay include: a semiconductor substrate including a plurality ofintegrally formed capacitors; and a separate interconnect structurecoupled to the semiconductor substrate, wherein the separateinterconnect structure is configurable to electrically couple two ormore of the plurality of integrally formed capacitors together in aparallel configuration.

According to various aspects there is provided a configurablecapacitance system. In some aspects, the configurable capacitance systemmay include: an electronic package; a multi-capacitor device disposedwithin the electronic package, the multi-capacitor device having asemiconductor substrate including a plurality of integrally formedcapacitors; an integrated circuit (IC) disposed within the electronicpackage, the IC operable to perform a circuit function; and aninterconnect structure forming a portion of the electronic package,wherein the interconnect structure is configurable to electricallycouple two or more of the plurality of integrally formed capacitorstogether in a parallel configuration, and to couple the parallelconfiguration to the IC.

According to various aspects there is provided a configurablecapacitance device. In some aspects, configurable capacitance device mayinclude: a semiconductor substrate including a plurality of integrallyformed capacitors; and a separate interconnect structure coupled to thesemiconductor substrate, wherein the separate interconnect structure isconfigurable to electrically couple two or more of the plurality ofintegrally formed capacitors together in at least one of a seriesconfiguration or a parallel configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments in accordance with the present disclosure will bedescribed with reference to the drawings, in which:

FIG. 1A is a diagram illustrating a representative example of aconfigurable capacitance chip according to some aspects of the presentdisclosure;

FIG. 1B is a diagram illustrating a side view of the representativeexample of the configurable capacitance chip in FIG. 1A according tosome aspects of the present disclosure.

FIG. 1C is a diagram illustrating a side view of another representativeexample of a configurable capacitance chip according to some aspects ofthe present disclosure.

FIG. 2 is a diagram illustrating another representative example of aconfigurable capacitance chip according to some aspects of the presentdisclosure;

FIG. 3A is a diagram illustrating a representative example of aconfigurable capacitance chip having a sense terminal according to someaspects of the present disclosure;

FIG. 3B is a simplified schematic diagram illustrating an electricalconnection of the sense terminal internal to the configurablecapacitance chip in FIG. 3A according to some aspects of the presentdisclosure;

FIG. 4 is a diagram illustrating an example of a configurablecapacitance chip within an electronic package according to some aspectsof the present disclosure;

FIG. 5 is a simplified schematic diagram illustrating example circuitconnections for an application of a configurable capacitance chipaccording to some aspects of the present disclosure;

FIG. 6 is a simplified schematic diagram illustrating an example of someparasitic inductances of an electronic package according to some aspectsof the present disclosure;

FIG. 7 is a simplified schematic diagram illustrating another example ofsome parasitic inductances of an electronic package according to someaspects of the present disclosure;

FIG. 8 is a diagram illustrating a representative example of aconfigurable capacitance-inductance chip according to some aspects ofthe present disclosure;

FIG. 9 is a simplified schematic diagram illustrating an exampleapplication of configurable capacitance-inductance chip according tosome aspects of the present disclosure;

FIG. 10 is a diagram illustrating a representative example of aconfigurable capacitance-resistance chip according to some aspects ofthe present disclosure;

FIG. 11 is a diagram illustrating a representative example of aconfigurable capacitance-resistance-inductance chip according to someaspects of the present disclosure; and

FIG. 12 is a flowchart illustrating an example of a method for making aconfigurable capacitance device according to some aspects of the presentdisclosure.

DETAILED DESCRIPTION

While certain embodiments are described, these embodiments are presentedby way of example only, and are not intended to limit the scope ofprotection. The apparatuses, methods, and systems described herein maybe embodied in a variety of other forms. Furthermore, various omissions,substitutions, and changes in the form of the example methods andsystems described herein may be made without departing from the scope ofprotection.

Discrete capacitors may be used for a variety of applications. One suchapplication is decoupling capacitors used to reduce voltage ripple andnoise at input and output voltage lines of integrated circuits, forexample, but not limited to, voltage regulators. As integrated circuitsbecome increasingly miniaturized with circuit components beingintegrated on-chip, high density, small footprint capacitors with lowEquivalent Series Resistance (ESR) and Equivalent Series Inductance(ESL) requirements that can be placed close to the integrated circuitsare needed.

Aspects of the present disclosure may provide a method for configuring adesired amount of capacitance on a single chip. The configurablecapacitance chip may be fabricated using standard semiconductorprocessing techniques. A configurable capacitance chip can provideflexibility and cost advantages as compared to placing multiplecapacitors on a printed circuit board (PCB) or integrated circuit (IC)package. The configurable capacitance chip may be fabricated at lowercost as compared to the cost of multiple discrete capacitors, and canprovide the ability to configure capacitor characteristics such as ESRand ESL at the package level. More specifically, in some embodiments astandardized capacitance chip can be used in different applicationswhere the number and characteristics of capacitors formed by thecapacitance chip are configured by changing electrical interconnects onthe package substrate to which the capacitance chip is connected. Inaddition, the configurable capacitance chip may occupy less space on aPCB compared to discrete capacitors. The configurable capacitance chipmay be applicable to any application where multiple capacitors arerequired.

FIG. 1A is a diagram illustrating a representative example of aconfigurable capacitance chip 100 according to some aspects of thepresent disclosure. FIG. 1B is a diagram illustrating a side view of therepresentative example of the configurable capacitance chip 100 in FIG.1A according to some aspects of the present disclosure. Referring toFIGS. 1A and 1B, the configurable capacitance chip 100 may include aplurality of capacitors 110 fabricated on a first surface 122 of asubstrate 120. Each capacitor 110 may be electrically connected to apair of contacts, referred to herein as chip bumps 140, fabricated onthe first surface 122 of the substrate 120. The chip bumps 140 may be,for example, solder bumps.

In some embodiments, a range of capacitance for each integratedcapacitor can be between 10 and 10,000 nanofarads, in another embodimentcan be between 50 and 5,000 nanofarads and in one embodiment between 50and 500 nanofarads. In some embodiments, multiple capacitors 110 may becombined to provide larger or smaller capacitance values. The combinedcapacitors may be referred to as capacitor banks 112, 114. The capacitorbanks 112, 114 may be formed, for example, by electrical connectionsfabricated on the first surface 122 of the substrate 120, by electricalconnections fabricated on a substrate of an IC package to which theconfigurable capacitance chip 100 is attached, by traces on a PCB towhich the IC package is attached, or by some combination. The electricalconnections may be formed to provide parallel connections of capacitors,series connections of capacitors, or series-parallel combinations ofcapacitors.

FIG. 1C is a diagram illustrating a side view of another representativeexample of a configurable capacitance chip 150 according to some aspectsof the present disclosure. Referring FIG. 1C, the configurablecapacitance chip 150 may include a plurality of capacitors 155fabricated on a first surface 162 of a substrate 160. Each capacitor 155may be electrically connected to a pair of contacts 170 fabricated onthe first surface 162 of the substrate 160. The contacts 170 fabricatedon the first surface 162 of the substrate 160 may be electricallyconnected to contacts, referred to herein as chip bumps 180, fabricatedon the second surface 164 of the substrate 160. The chip bumps 180 maybe, for example, solder bumps. In some embodiments, multiple capacitors110 may be combined into banks to provide larger or smaller capacitancevalues by electrical connections by electrical connections fabricated onthe second surface 164 of the substrate 160, by electrical connectionsfabricated on a substrate of an IC package to which the configurablecapacitance chip 150 is attached, by traces on a PCB to which the ICpackage is attached, or by some combination.

While FIG. 1A illustrates two banks 112, 114 having equal numbers ofcapacitors in each bank, the banks may be of various sizes depending onintended applications. In some implementations, the capacitors 110 maynot be grouped in banks. Electrical connections between the capacitorsare not limited to the capacitors within a bank of capacitors inimplementations where capacitor banks are fabricated.

It should be appreciated that FIGS. 1A, 1B, and 1C are stylizedrepresentations of the configurable capacitance chip according to someaspects of the present disclosure, and are provided for ease ofexplanation. The figures are not meant to illustrate representativedimensions of any elements of the configurable capacitance chip.Further, the number of illustrated capacitors is merely representativeand does not limit the number of capacitors or their relative placementprovided by various embodiments. In addition, while the capacitorcontacts 140 are labeled Vout and Vss in FIGS. 1A, the labels are merelyrepresentative and are not to be construed as requiring the capacitorcontacts 140 to be connected to Vout and Vss voltages.

FIG. 2 is a diagram illustrating another representative example of aconfigurable capacitance chip 200 according to some aspects of thepresent disclosure. Referring to FIG. 2 , the configurable capacitancechip including four different banks 210-240 of capacitors areillustrated. As shown in FIG. 2 , each bank 210-240 of capacitors mayinclude different numbers of capacitors. In addition, the capacitors maybe fabricated in different orientations. For example, the capacitors 212in the first bank 210 are fabricated in a vertical direction, while thecapacitors 222 in the second bank 220 are fabricated in a horizontaldirection. A capacitor bank may include capacitors fabricated in bothhorizontal and vertical directions. The configurable capacitance chip200 may be configured as a single capacitor (e.g., all capacitorscoupled together) or as multiple capacitors (e.g., groups of capacitorscoupled together).

It should be appreciated that FIG. 2 is a stylized representation of theconfigurable capacitance chip according to some aspects of the presentdisclosure, and is provided for ease of explanation. The figure is notmeant to illustrate representative dimensions of any elements of theconfigurable capacitance chip. Further, the number of illustratedcapacitors is merely representative and does not limit the number ofcapacitors or their relative placement provided by various embodiments.In addition, while the capacitor terminals are labeled Vout and Vss inFIGS. 2 , the labels are merely representative and are not to beconstrued as requiring the capacitor terminals to be connected to Voutand Vss voltages.

FIG. 3A is a diagram illustrating a representative example of aconfigurable capacitance chip 300 having a sense terminal according tosome aspects of the present disclosure. FIG. 3B is a simplifiedschematic diagram illustrating an electrical connection of the senseterminal internal to the configurable capacitance chip 300 in FIG. 3Aaccording to some aspects of the present disclosure. Referring to FIGS.3A and 3B, the configurable capacitance chip 300 may include a voltagesense terminal Vosns 340. The voltage sense terminal Vosns 340 may beconnected externally to a solder bump (e.g., a solder bump 140) of theconfigurable capacitance chip 300, and internally to the configurablecapacitance chip 300 at the capacitor 310 and may be a connection pointof a combination of capacitors the configurable capacitance chip 300.One or more voltage sense terminal Vosns 340 solder bumps may be usedper capacitor bank or group of capacitors.

The voltage sense terminal Vosns 340 may enable voltage sensing thatminimizes the effect of the ESR 360 and ESL 350 of the capacitor orcombination of capacitors. For example, in a voltage regulatorapplication, the voltage sense terminal Vosns 340 may minimize theeffects of the parasitic resistance and inductance of the Voutconfigurable capacitive chip bumps and/or Vout package balls and on thecontrol loop of the voltage regulator. The inductors of the voltageregulator may be terminated on Vout bumps while the control loopfeedback can be taken from the Vout sense bump Vosns 340.

FIG. 4 is a diagram illustrating an example of a configurablecapacitance chip within an electronic package according to some aspectsof the present disclosure. As illustrated in FIG. 4 , an electronicpackage 410 may be mounted on a PCB 420 with a ball grid array 430 orother solder connections connecting a package substrate 440 to the PCB420. An integrated circuit 450, for example, a voltage regulator, and aconfigurable capacitance chip 460 may be mounted on the packagesubstrate 440 within the electronic package 410 using solder bumps 470.Electrical connections between the integrated circuit 450 and theconfigurable capacitance chip 460 may be formed through the solder bumpconnections to the package substrate 440. Electrical connections betweenthe integrated circuit 450 and electrical connections to theconfigurable capacitance chip 460 (e.g., Vout, Vss, Vosns) may bebrought out to the PCB via the ball grid array 430 or other solderconnections connecting a package substrate 440 to the PCB 420.

Electrical connections from integrated circuit 450 and the configurablecapacitance chip 460 to the PCB 420 may be formed by the solder bumps470 and the ball grid array 430. In some implementations, electricalconnections between the capacitors on the configurable capacitance chip460 may be fabricated on the substrate of the configurable capacitancechip 460, on a substrate 440 of the electronic package 410 to which theconfigurable capacitance chip 460 is attached, by traces on a PCB 420 towhich the electronic package 410 is attached, or by some combination ofthe electrical connections.

As used herein, the terms “ball” or “package ball” may refer to anelectrical connection (e.g., balls 430) between an integrated circuitpackage, for example, but not limited to, Quad Flat No-lead (QFN)packages, quad flat packs (QFPs), small outline ICs (SOICs), or othertypes of electronic packages, and a PCB. As used herein, the terms“bump” or “chip bump” may refer to a solder bump connection (e.g., bumps470) between an integrated circuit chip 450 or configurable capacitancechip 460 and an electronic package substrate 440, or in a chip on board(COB) implementation, between the integrated circuit or configurablecapacitance chip and the PCB 420.

Either the substrate 440 of the electronic package 410, the PCB 420, orboth, can be used to connect any number of the chip capacitors togetherto form one or more capacitors having a particular capacitance, ESR andESL value. By changing the electrical traces on either structure fromapplication to application, a standardized capacitor chip can beconfigured for multiple applications. For example, in one application,all of the capacitors can be coupled in parallel to provide one largecapacitor. In another application, one capacitor may be used for an ICdecoupling capacitor, a first group of 10 capacitors may be coupled inparallel to form a decoupling capacitor for a first voltage regulator, asecond group of 10 capacitors may be coupled in parallel to form adecoupling capacitor for a second voltage regulator decouplingcapacitor. The decoupling capacitors formed by the parallel combinationscan provide suitable capacitance, ESR, and ESL values for the first andthe second voltage regulators.

FIG. 5 is a simplified schematic diagram illustrating example circuitconnections for an application of a configurable capacitance chipaccording to some aspects of the present disclosure. As shown in FIG. 5, an application of this configurable capacitor chip may be a dualchannel voltage regulator (VR) 500 having a capacitor for each output.

Referring to FIG. 5 , the dual channel voltage regulator may include avoltage regulator circuit 510 having a first voltage regulator VR1 and asecond voltage regulator VR2. The first voltage regulator VR1 maygenerate an output current through a first set of inductors 515 to aload 525. The second voltage regulator VR 2 may generate an outputcurrent through a second set of inductors 520 to the load 525. Theconfigurable capacitance chip 530 a, 530 b according to the presentdisclosure may be configured to provide an input capacitor 532 andoutput capacitors 534, 536 for the voltage regulator circuit 510.

Printed circuit wiring and solder connections to electronic packagescontribute parasitic inductances to a circuit. According to some aspectsof the present disclosure, the package ball inductance may beincorporated into the output inductor of a circuit, for example avoltage regulator circuit. FIG. 6 is a simplified schematic diagramillustrating an example of some parasitic inductances of an electronicpackage according to some aspects of the present disclosure.

Referring to FIG. 6 , an electronic package 620 may be mounted on thePCB 610 and electrically connected to the PCB 610 via package balls aspreviously described. A configurable capacitance chip 630 may be mountedwithin the electronic package 620 via chip bumps as previouslydescribed. A voltage regulator circuit (not shown) may include inductors615 on a PCB 610. The inductors may be, for example, but not limited to,discrete component inductors, inductor traces formed on a surface of thePCB 610, inductor traces integrated within multiple layers of the PCB610, etc.

One or more package balls 622 per inductor may be included as part ofeach of the PCB inductors 615. Incorporating the package ball inductancewith the PCB inductors can reduce the effective ESL and ESR of thecapacitor 632 affecting the control loop by sensing the output voltagevia the Vosns package ball 624 as shown. The Vout and Vss connectionsfor the voltage regulator circuit may be brought out via the packageVout ball 626 and the package Vss ball 628. The Vout connection via thepackage Vout ball 626 may similarly reduce the output ripple by reducingthe effective ESR and ESL of the capacitor 632.

In some embodiments one or more inductors may be integrated within theelectronic package substrate. FIG. 7 is a simplified schematic diagramillustrating another example of some parasitic inductances of anelectronic package according to some aspects of the present disclosure.Referring to FIG. 7 , a configurable capacitance chip 730 may be mountedwithin the electronic package 720 via chip bumps as previouslydescribed. The electronic package 720 may be mounted on a PCB 710 viapackage balls as previously described. A voltage regulator circuit 705may be an integrated circuit included in the electronic package 720. Thevoltage regulator circuit 705 may be mounted within the electronicpackage 720 via chip bumps as previously described. Output inductors 715for the voltage regulator circuit 705 may be, for example, but notlimited to, discrete component inductors, inductor traces formed on asurface of the substrate of the electronic package 720, inductor tracesintegrated within multiple layers of the electronic package substrate,etc.

One or more chip bumps 732 per inductor may be included as part of eachof the output inductors 715. Incorporating the chip bump inductance withthe output inductors 715 can reduce the effective ESL and ESR of thecapacitor 734 affecting the control loop by sensing the output voltagevia the Vosns chip bump 724 as shown. The Vout and Vss connections forthe voltage regulator circuit may be brought out via the Vout chip bump732 and the Vss chip bump 738.

In accordance with some aspects of the present disclosure, variousembodiments of the configurable capacitance chip may include additionalconfigurable components such as resistors and inductors. FIG. 8 is adiagram illustrating a representative example of a configurablecapacitance-inductance chip 800 according to some aspects of the presentdisclosure. Referring to FIG. 8 , the configurablecapacitance-inductance chip 800 may include a plurality of capacitors810 and a plurality of inductors 820 fabricated on a first surface of asubstrate 830. Each capacitor 810 and each inductor 820 may beelectrically connected to a pair of contacts 840, 845, respectively,fabricated on the first surface of the substrate 830. The contacts 840,845 fabricated on the first surface of the substrate 830 may be referredto herein as chip bumps. The chip bumps may be, for example, solderbumps.

The bumps may be fabricated similarly to the bumps as described withrespect to FIG. 1 . Also, as described with respect to FIG. 1 , in someimplementations, the capacitors 810 and the inductors 820 may be groupedinto banks 850. In some implementations, the capacitors 810 and theinductors 820 may not be grouped into banks. In some implementations,the configurable capacitance-inductance chip 800 may include one or morevoltage sense terminals Vosns as described with respect to FIG. 3 .

In some embodiments, a range of capacitance for each integratedcapacitor can be between 10 and 10,000 nanofarads, in another embodimentcan be between 50 and 5,000 nanofarads and in one embodiment between 50and 500 nanofarads. In some embodiments, multiple capacitor 110 may becombined to provide larger or smaller capacitance values.

In some embodiments a range of inductance for each integrated inductorscan be between 1 picohenry and 100 nanohenrys, in another embodiment canbe between 100 picohenrys and 10 nanohenrys and in one embodimentbetween 1 and 5 nanohenrys.

It should be appreciated that FIG. 8 is a stylized representation of theconfigurable capacitance-inductance chip according to some aspects ofthe present disclosure, and is provided for ease of explanation. Thefigure is not meant to illustrate representative dimensions of anyelements of the configurable capacitance-inductance chip. Further, thenumber of illustrated capacitors and inductors are merely representativeand does not limit the number of capacitors and inductors or theirrelative placement provided by various embodiments. In addition, whilethe capacitor contacts 840 are labeled Vout and Vss in FIG. 8 , thelabels are merely representative and are not to be construed asrequiring the capacitor contacts 840 to be connected to Vout and Vssvoltages.

FIG. 9 is a simplified schematic diagram illustrating an exampleapplication of configurable capacitance-inductance chip according tosome aspects of the present disclosure. Referring to FIG. 9 , aconfigurable capacitance-inductance chip 930 may be mounted within theelectronic package 920 via chip bumps as previously described. Theelectronic package 920 may be mounted on a PCB via package balls aspreviously described. A voltage regulator circuit 905 may be anintegrated circuit included in the electronic package 920. The voltageregulator circuit 905 may be mounted within the electronic package 920via chip bumps as previously described. In some implementations, theconfigurable capacitance-inductance chip and the voltage regulatorcircuit may be mounted directly to the PCB via the chip bumps.

Output inductors and capacitors for the voltage regulator circuit 905may be provided by the inductors 932 and capacitors 934 of theconfigurable capacitance inductance chip 930. In some implementations,one or more chip bumps 917 per inductor may be included as part of eachof the output inductors 932. Incorporating the chip bump 917 inductancewith the output inductors 932 can reduce the effective ESL and ESR ofthe capacitor 934 affecting the control loop by sensing the outputvoltage via the Vosns chip bump 915 as shown.

FIG. 10 is a diagram illustrating a representative example of aconfigurable capacitance-resistance chip 1000 according to some aspectsof the present disclosure. Referring to FIG. 10 , the configurablecapacitance-resistance chip 1000 may include a plurality of capacitors1010 and a plurality of resistors 1020 fabricated on a first surface ofa substrate 1030. Each capacitor 1010 and each resistors 1020 may beelectrically connected to a pair of contacts 1040, 1045, respectively,fabricated on the first surface of the substrate 1030. The contacts1040, 1045 fabricated on the first surface of the substrate 1030 may bereferred to herein as chip bumps. The chip bumps may be, for example,solder bumps.

The bumps may be fabricated similarly to the bumps as described withrespect to FIG. 1 . Also, as described with respect to FIG. 1 , in someimplementations, the capacitors 1010 and the resistors 1020 may begrouped into banks 1050. In some implementations, the capacitors 1010and the resistors 1020 may not be grouped into banks. In someimplementations, the configurable capacitance-resistance chip 1000 mayinclude one or more voltage sense terminals Vosns as described withrespect to FIG. 3

In some embodiments, a range of capacitance for each integratedcapacitor can be between 10 and 10,000 nanofarads, in another embodimentcan be between 50 and 5,000 nanofarads and in one embodiment between 50and 500 nanofarads. In some embodiments, multiple capacitors 1010 may becombined to provide larger or smaller capacitance values.

In some embodiments, a range of resistance for each integrated resistorcan be between 50 ohms and ten thousand ohms. Other resistance rangesmay be possible. In some embodiments, multiple resistors 1020 may becombined to provide larger or smaller resistance values.

It should be appreciated that FIG. 10 is a stylized representation ofthe configurable capacitance-resistance chip according to some aspectsof the present disclosure, and is provided for ease of explanation. Thefigure is not meant to illustrate representative dimensions of anyelements of the configurable capacitance-resistance chip. Further, thenumber of illustrated capacitors and resistors are merely representativeand does not limit the number of capacitors and resistors or theirrelative placement provided by various embodiments. In addition, whilethe capacitor contacts 1040 are labeled Vout and Vss in FIG. 10 , thelabels are merely representative and are not to be construed asrequiring the capacitor contacts 1040 to be connected to Vout and Vssvoltages.

FIG. 11 is a diagram illustrating a representative example of aconfigurable capacitance-resistance-inductance chip 1100 according tosome aspects of the present disclosure. Referring to FIG. 11 , theconfigurable capacitance-resistance-inductance chip 1100 may include aplurality of capacitors 1110, a plurality of resistors 1120, and aplurality of inductors 1125 fabricated on a first surface of a substrate1130. Each capacitor 1110, each resistor 1120, and each inductor 1125may be electrically connected to a pair of contacts 1140, 1145, 1148,respectively, fabricated on the first surface of the substrate 1130.

The contacts 1140, 1145, 1148 fabricated on the first surface of thesubstrate 1130 may be referred to herein as chip bumps. The chip bumpsmay be, for example, solder bumps. The bumps may be fabricated similarlyto the bumps as described with respect to FIG. 1 . Also, as describedwith respect to FIG. 1 , in some implementations, the capacitors 1110,the resistors 1120, and the inductors 1125 may be grouped into banks1150. In some implementations, the capacitors 1110, the resistors 1120,and the inductors 1125 may not be grouped into banks. In someimplementations, the configurable capacitance-resistance-inductance chip1100 may include one or more voltage sense terminals Vosns as describedwith respect to FIG. 3 .

In some embodiments, a range of capacitance for each integratedcapacitor can be between 10 and 10,000 nanofarads, in another embodimentcan be between 50 and 5,000 nanofarads and in one embodiment between 50and 500 nanofarads. In some embodiments, multiple capacitors 1110 may becombined to provide larger or smaller capacitance values.

In some embodiments, a range of resistance for each integrated resistorcan be between 50 ohms and ten thousand ohms. Other resistance rangesmay be possible. In some embodiments, multiple resistors 1120 may becombined to provide larger or smaller capacitance values.

In some embodiments a range of inductance for each integrated inductorscan be between 1 picohenry and 100 nanohenrys, in another embodiment canbe between 100 picohenrys and 10 nanohenrys and in one embodimentbetween 1 and 5 nanohenrys. In some embodiments, multiple inductors 1125may be combined to provide larger or smaller inductance values.

It should be appreciated that FIG. 11 is a stylized representation ofthe configurable capacitance-resistance-inductance chip according tosome aspects of the present disclosure, and is provided for ease ofexplanation. The figure is not meant to illustrate representativedimensions of any elements of the configurablecapacitance-resistance-inductance chip. Further, the number ofillustrated capacitors, resistors, and inductors are merelyrepresentative and does not limit the number of capacitors, resistors,and inductors or their relative placement provided by variousembodiments. In addition, while the capacitor contacts 1140 are labeledVout and Vss in FIG. 11 , the labels are merely representative and arenot to be construed as requiring the capacitor contacts 1140 to beconnected to Vout and Vss voltages.

FIG. 12 is a flowchart illustrating an example of a method 1200 formaking a configurable integrated circuit (IC) capacitive deviceaccording to some aspects of the present disclosure. Referring to FIG.12 , at block 1210, a capacitive device may be formed. The capacitivedevice may be fabricated using standard semiconductor processingtechniques. A plurality of capacitors may be fabricated on a firstsurface of a substrate. Each capacitor may be electrically connected toa pair of contacts fabricated on the first surface of the substrate 120.The contacts fabricated on the first surface of the substrate may bereferred to herein as chip bumps. The chip bumps may be, for example,solder bumps.

At optional block 1220, electrical connections between capacitors may beformed on the substrate of the capacitive device. In some embodiments,multiple capacitors may be combined to provide larger or smallercapacitance values. The combined capacitors may be referred to ascapacitor banks. The capacitor banks may be formed, for example, byelectrical connections fabricated on the second surface of thesubstrate.

At block 1230, electrical connections between capacitors may be formedon a substrate of an electronic package. The additional electricalconnections may be fabricated as circuit traces on the substrate of theelectronic package into which the capacitive device will be integrated.Conductive traces on the substrate of the electronic package may provideelectrical connections between the chip bumps to configure thecapacitors on the capacitive device.

At block 1240, the capacitive device may be integrated into theelectronic package. Electrical connections may be formed between thesubstrate of the capacitive device and the substrate of the electronicpackage. For example, the solder bumps on the substrate of thecapacitive device may be electrically connected to the conductive traceson the substrate of the electronic package. The electrical connectionsbetween the capacitors formed by the conductive traces on the substrateof the electronic package may form the desired capacitance values.

At optional block 1250, additional electrical connections betweencapacitors may be formed conductive traces on the PCB to which theelectronic package is attached. The combined electrical connectionsbetween the capacitors formed by the conductive on the PCB andconductive traces on the substrate of the electronic package may formthe desired capacitance values.

The specific operations illustrated in FIG. 12 provide a particularmethod for making a configurable integrated circuit (IC) capacitoraccording to an embodiment of the present disclosure. Other sequences ofoperations may also be performed according to alternative embodiments.For example, alternative embodiments of the present disclosure mayperform the operations outlined above in a different order. Moreover,the individual operations illustrated in FIG. 12 may include multiplesub-operations that may be performed in various sequences as appropriateto the individual operation. Furthermore, additional operations may beadded or removed depending on the particular applications.

According to some aspects of the present disclosure, a configurablecapacitors in an integrated package is provided. As used below, anyreference to a series of examples is to be understood as a reference toeach of those examples disjunctively (e.g., “Examples 1-4” is to beunderstood as “Examples 1, 2, 3, or 4”).

Example 1 is a configurable capacitance device, having a semiconductorsubstrate including a plurality of integrally formed capacitors; and aseparate interconnect structure coupled to the semiconductor substrate,wherein the separate interconnect structure is configurable toelectrically couple two or more of the plurality of integrally formedcapacitors together in a parallel configuration.

Example 2 is the configurable capacitance device of example 1, whereinthe separate interconnect structure is configurable to couple two ormore of the plurality of integrally formed capacitors together to form afirst capacitor having a first combined capacitance, the separateinterconnect structure is configurable to couple two or more of theplurality of integrally formed capacitors together to form a secondcapacitor having a second combined capacitance; and the first combinedcapacitance is greater than the second combined capacitance.

Example 3 is the configurable capacitance device of example(s) 1 or 2,wherein the separate interconnect structure is configurable to coupleeach the plurality of integrally formed capacitors together to form asingle capacitor having a combined capacitance.

Example 4 is the configurable capacitance device of example(s) 1-3,wherein: the two or more of the plurality of integrally formedcapacitors coupled together in a parallel configuration comprise a firstcapacitor having a first combined capacitance, and the separateinterconnect structure is configurable to couple two or more of theplurality of integrally formed capacitors together in a seriesconfiguration to form a second capacitor having a second combinedcapacitance.

Example 5 is the configurable capacitance device of example(s) 1-4,wherein the separate interconnect structure comprises a plurality ofelectrical conductors configured to extend between two or more of theplurality of integrally formed capacitors.

Example 6 is the configurable capacitance device of example(s) 1-5,wherein the separate interconnect structure is formed on a substrate ofan integrated circuit (IC) package to which the semiconductor substrateis attached, by traces on a printed circuit board to which the ICpackage is attached, or by a combination thereof.

Example 7 is the configurable capacitance device of example(s) 1-6,further including a sense conductor that is electrically connected to atleast one of the plurality of integrally formed capacitors on thesemiconductor substrate.

Example 8 is the configurable capacitance device of example(s) 1-7,wherein the semiconductor substrate further comprises a plurality ofinductors, wherein the separate interconnect structure is configurableto electrically couple two or more of the plurality of inductorstogether to form a single inductor having a combined inductance.

Example 9 is the configurable capacitance device of example(s) 1-8,wherein the separate interconnect structure is configurable toelectrically couple at least one of the plurality of integrally formedcapacitors together with at least one of the plurality of inductors toform an inductor-capacitor circuit.

Example 10 is the configurable capacitance device of example(s) 1-9,wherein: the semiconductor substrate further comprises a plurality ofresistors, and the separate interconnect structure is configurable toelectrically couple two or more of the plurality of resistors togetherto form a single resistor having a combined resistance.

Example 11 is the configurable capacitance device of example(s) 1-10,wherein: the semiconductor substrate includes a plurality of firstinterconnects, wherein each pair of the plurality of first interconnectsis coupled to a respective capacitor of the plurality of integrallyformed capacitors, and the separate interconnect structure includes aplurality of second interconnects corresponding with and coupled to theplurality of first interconnects.

Example 12 is a configurable capacitance system, including: anelectronic package; a multi-capacitor device disposed within theelectronic package, the multi-capacitor device having a semiconductorsubstrate including a plurality of integrally formed capacitors; anintegrated circuit (IC) disposed within the electronic package, the ICoperable to perform a circuit function; and an interconnect structureforming a portion of the electronic package, wherein the interconnectstructure is configurable to electrically couple two or more of theplurality of integrally formed capacitors together in a parallelconfiguration, and to couple the parallel configuration to the IC.

Example 13 is the configurable capacitance system of example 12,wherein: the interconnect structure is configurable to couple two ormore of the plurality of integrally formed capacitors together to form afirst capacitor having a first combined capacitance, the interconnectstructure is configurable to couple two or more of the plurality ofintegrally formed capacitors together to form a second capacitor havinga second combined capacitance; and the first combined capacitance isgreater than the second combined capacitance.

Example 14 is the configurable capacitance system of example(s) 12 or13, wherein the interconnect structure is configurable to couple eachthe plurality of integrally formed capacitors together to form a singlecapacitor having a combined capacitance.

Example 15 is the configurable capacitance system of example(s) 12-14,wherein: the two or more of the plurality of integrally formedcapacitors coupled together in a parallel configuration comprise a firstcapacitor having a first combined capacitance, and the interconnectstructure is configurable to couple two or more of the plurality ofintegrally formed capacitors together in a series configuration to forma second capacitor having a second combined capacitance.

Example 16 is the configurable capacitance system of example(s) 12-15,wherein the interconnect structure comprises a plurality of electricalconductors configured to extend between two or more of the plurality ofintegrally formed capacitors, and between the two or more of theplurality of integrally formed capacitors and the IC.

Example 17 is the configurable capacitance system of example(s) 12-16,wherein interconnect structure is formed on a substrate of an integratedcircuit (IC) package to which the semiconductor substrate is attached,by traces on a printed circuit board to which the IC package isattached, or by a combination thereof.

Example 18 is the configurable capacitance system of claims 12-17,further including: forming a sense conductor that is electricallyconnected to at least one of the plurality of capacitors and to a sensecontact formed on the mating surface of the semiconductor substrate.

Example 19 is configurable capacitance device, including: asemiconductor substrate including a plurality of integrally formedcapacitors; and a separate interconnect structure coupled to thesemiconductor substrate, wherein the separate interconnect structure isconfigurable to electrically couple two or more of the plurality ofintegrally formed capacitors together in at least one of a seriesconfiguration or a parallel configuration.

Example 20 is the method of example 19, further including: a senseconductor that is electrically connected to at least one of theplurality of integrally formed capacitors on the semiconductorsubstrate.

The examples and embodiments described herein are for illustrativepurposes only. Various modifications or changes in light thereof will beapparent to persons skilled in the art. These are to be included withinthe spirit and purview of this application, and the scope of theappended claims, which follow.

1. An electronic device comprising: a semiconductor substrate includinga first integrally formed capacitor having first and second terminalsformed at a bottom surface of the semiconductor substrate, thesemiconductor substrate including a second integrally formed capacitorhaving third and fourth terminals formed at the bottom surface of thesemiconductor substrate; and an interconnect board attached to thesemiconductor substrate and including: first, second, third and fourthelectrical interconnects formed at a first surface wherein the firstelectrical interconnect is electrically connected to the first terminal,the second electrical interconnect is electrically connected to thesecond terminal, the third electrical interconnect is electricallyconnected to the third terminal and the fourth electrical interconnectis electrically connected to the fourth terminal; a plurality of secondelectrical interconnects formed at a second surface opposite the firstsurface; and a plurality of electrical conductors coupling the first,second, third and fourth electrical interconnects to two of the secondelectrical interconnects.
 2. The electronic device of claim 1, whereinthe plurality of electrical conductors couple the first capacitor inparallel with the second capacitor.
 3. The electronic device of claim 1,wherein the plurality of electrical conductors couple the firstcapacitor in series with the second capacitor.
 4. The electronic deviceof claim 1, wherein the interconnect board comprises a printed circuitboard.
 5. The electronic device of claim 1, wherein the plurality ofsecond electrical interconnects comprise spherical interconnectsarranged to be soldered to a separate electronic device.
 6. Theelectronic device of claim 1, wherein the first electrical interconnectis electrically connected to the first terminal, the second electricalinterconnect is electrically connected to the second terminal, the thirdelectrical interconnect is electrically connected to the third terminaland the fourth electrical interconnect is electrically connected to thefourth terminal via soldered interfaces.
 7. An electronic devicecomprising: a substrate including a plurality of integrally formedcapacitors, each capacitor having respective electrical terminals formedat a bottom surface of the substrate; and an interconnect board attachedto the substrate and including: a plurality of first electricalinterconnects formed at a first surface and electrically coupled to theelectrical terminals; a plurality of second electrical interconnectsformed at a second surface opposite the first surface; and a pluralityof electrical conductors coupling at least two of the integrally formedcapacitors together.
 8. The electronic device of claim 7, wherein theplurality of electrical conductors couple the at least two integrallyformed capacitors together in parallel.
 9. The electronic device ofclaim 7, wherein the plurality of electrical conductors couple the atleast two integrally formed capacitors together in series.
 10. Theelectronic device of claim 7, wherein the interconnect board comprises aprinted circuit board.
 11. The electronic device of claim 7, wherein theplurality of second electrical interconnects comprise sphericalinterconnects arranged to be soldered to a separate electronic device.12. The electronic device of claim 7, wherein the plurality of firstelectrical interconnects are electrically coupled to the electricalterminals via soldered interfaces.
 13. A method of making an electronicdevice, the method comprising: forming a substrate including a pluralityof integral capacitors, each capacitor having respective electricalterminals disposed at a bottom surface of the substrate; and forming aninterconnect board and attaching the interconnect board to thesubstrate, wherein the interconnect board comprises: a plurality offirst electrical interconnects disposed at a first surface andelectrically coupled to the electrical terminals; a plurality of secondelectrical interconnects disposed at a second surface opposite the firstsurface; and a plurality of electrical conductors arranged to couple atleast two of the integral capacitors together.
 14. The method of claim13, wherein the plurality of electrical conductors couple a firstcapacitor of the plurality of integral capacitors in parallel with asecond capacitor of the plurality of integral capacitors.
 15. The methodof claim 13, wherein the plurality of electrical conductors couple afirst capacitor of the plurality of integral capacitors in series with asecond capacitor of the plurality of integral capacitors.
 16. The methodof claim 13, wherein the interconnect board comprises a printed circuitboard.
 17. The method of claim 13, wherein the plurality of secondelectrical interconnects comprise spherical interconnects arranged to besoldered to a separate electronic device.
 18. The method of claim 13,wherein the plurality of first electrical interconnects are electricallycoupled to the electrical terminals via soldered interfaces.
 19. Themethod of claim 13, wherein the interconnect board is a firstinterconnect board arranged to couple a first and a second capacitor ofthe plurality of integral capacitors in parallel, and wherein thesubstrate is configured to be attached to a second interconnect boardarranged to couple the first and the second capacitors of plurality ofintegral capacitors in series.
 20. The method of claim 13, wherein thesubstrate further comprises an inductor.